`timescale 100ns / 100ps

                       
module tb_matrix_ctrl
    (   output logic                    clk
        );
//*********************** КОНСТАНТЫ ****************************************************************
    integer frame_length_lp = 20_000_000 ;
//*********************** СОЗДАНИЕ И ОПИСАНИЕ ПЕРЕМЕННЫХ *******************************************
    logic           reset_n;
    
    logic           start;
    logic           vldata, vrdata, vsample, vrsync, vlsync, vhdata, vhsync, vclamp;
    logic           row_end;
    logic [15:0]    data;
    logic           wre;
    logic [31:0]    addr;
    
//********************** БЛОК НЕПРЕРЫВНЫХ НАЗНАЧЕНИЙ ASSIGN ****************************************
    assign not_vldata = ~vldata;

//********************** ОПИСАНИЕ ПОДКЛЮЧАЕМЫХ БЛОКОВ ***********************************************

mod_matrix_ctrl
mod_matrix_ctrl_inst
    (   .reset_n            (reset_n),
        .clk                (clk),

        .start_i            (start),

        .period_frame       (frame_length_lp),
        .length_vldata      (100 * 2),
        .length_vrdata      (100 * 2),
        .length_exp         (100000),//frame_length_lp / 120),83300
        .length_vhdata      (100 * 2),
        .period_vhsync      (100 * 2),
        .delay_vhdata       (0),
        .delay_vsample      (0),
        .length_vsample     (100 * 1),
        
        .data_i             (0),
        .vldata_o           (vldata),
        .vlsync_o           (vlsync),

        .vrdata_o           (vrdata),
        .vrsync_o           (vrsync),

        .vhdata_o           (vhdata),
        .vhsync_o           (vhsync),
        
        .vsample_o          (vsample),
        .vclamp_o           (vclamp),
        
        .data_o             (data),
        .wre_o              (wre),
        .addr_o             (addr)
    );
  
// ********************* БЛОКИ ИНИЦИАЛИЗАЦИИ *******************************************************
    initial begin
        reset_n = 0;
    #25  reset_n = 1;
    end
    
    initial begin        // CLK
        clk = 0;
        forever #5ns clk = ~clk;
    end
    
    initial begin        // CLK

        // repeat (50) begin
            start = 0;
            #500;
            start = 1;
            #550;
            start = 0;
        // end;
    end    
endmodule